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A* * 'F'<'F'<'F'F'<&8 "('F'<'F'<'F'F'<&8 "( " " " " " " " " "'F'<'F'<'F'F'<&8 "('F'<'F'<'F'F'<&8 "( 8 8% 8% "% 8 8 2 8 2 * 8 8% 8% " 8 8 8%%% 8 8 8%%% 7sisfb: Bad EDID header
3sisfb: YPbPr not supported
FPDI-2 D&P 2 [none of the supported] 6sisfb: CRT%d DDC supported
6%s %s SCART output
6%s %s SVIDEO output
6%s %s COMPOSITE output
6%s SVIDEO output
6%s CVBS output
6%s SCART output
6%s SiS301 %s
6%s SiS301B-DH %s
6%s SiS301B %s
6%s SiS301C %s
6%s SiS301LV %s
6%s SiS302LV %s
6%s SiS301C(P4) %s
6%s SiS302B %s
6%s LVDS transmitter
6%s Chrontel TV encoder
video bridge none 4 "%s" (for %s %s)
3sisfb: Unsupported depth %d not enabled (no auto-max) disabled enabled (auto-max) enabled 6sisfb: Video ROM %sfound
Z9 detected
3sisfb: Failed to POST card
sisfb FB sisfb MMIO 7sisfb: Failed to add MTRRs
sisfb: no valid timing data
%u %u %u %u %ux%ux%u %u %u %u %u %u %ux%ux8 3sisfb: Invalid mode '%s'
sisfb 7sisfb: Module unloaded
SiS 300/305 SiS 540 SiS 630 SiS 315H SiS 315 SiS 315PRO SiS 55x SiS 650 SiS 330 SiS 660 XGI Z7 XGI V3XT/V5/V8 Mitachi 0x1002 Mitac 7521P 2.00.07 09/27/2002-13:38:25 Barco iQ R200L/300/400 BARCO_1366 iQ G200L/300/400/500 BARCO_1024 Inventec (Compaq) 3017cl/3045US COMPAQ_1280 Clevo L285/L287 (Version 1) CLEVO_L28X_1 L285/L287 (Version 2) CLEVO_L28X_2 D400S/D410S/D400H/D410H CLEVO_D4X0 D22ES/D27ES CLEVO_D2X0ES Uniwill N243S9 UNIWILL_N243S9 N35BS1 UNIWILL_N35BS1 1.09.2c ECS A928 ECS_A928 1.11.27a Asus L3000D/L3500D ASUS_L3X00 1.10.9k Acer Aspire 1700 ACER_ASPIRE1700 1.10.7w Compal ??? (V1) COMPAL_1400_1 1.10.7x ??? (V2) COMPAL_1400_2 1.10.8o A2H (V1) ASUS_A2H_1 1.10.8q A2H (V2) ASUS_A2H_2 Generic LVDS/Parallel 848x480 PANEL848x480 LVDS/Parallel 856x480 PANEL856x480 3Could not find mode %x
6sisfb: EDID version %d not supported
6sisfb: WARNING: Monitor does not support separate syncs
6sisfb: Restoring of text mode not supported yet
3sisfb: HiVision not supported
3sisfb: PALM/PALN/NTSCJ not supported
6sisfb: Detected LCD PDC 0x%02x
6sisfb: Using LCD PDC 0x%02x
6sisfb: Detected LCD PDC 0x%02x (for LCD=CRT2)
6sisfb: Detected LCD PDC1 0x%02x (for LCD=CRT1)
6sisfb: Using LCD PDC 0x%02x (for LCD=CRT2)
6sisfb: Using LCD PDC1 0x%02x (for LCD=CRT1)
7sisfb: Invalid panel ID (%02x), assuming 1024x768, RGB18
7sisfb: Detected %dx%d flat panel
7sisfb: Identified [%s %s], special timing applies
7sisfb: [specialtiming parameter name: %s]
6sisfb: CRT%d DDC probing failed
6sisfb: CRT%d DDC level: %s%s%s%s
6sisfb: Monitor range H %d-%dKHz, V %d-%dHz, Max. dotclock %dMHz
6sisfb: CRT%d DDC EDID corrupt
6sisfb: VESA D&P and FPDI-2 not supported yet
6sisfb: CRT%d DDC reading failed
6%s secondary VGA connection
6%s %s YPbPr component output
6sisfb: TV detection unreliable - test results varied
sisfb: Chrontel: Detected TV connected to 6%s Trumpion Zurac LCD scaler
6%s Conexant external device
3sisfb: Invalid CRT2 type: %s
7sisfb: Special timing disabled
6sisfb: Special timing for %s %s forced ("%s")
4sisfb: Invalid SpecialTiming parameter, valid are: 4 "none" (to disable special timings)
6sisfb: Memory heap starting at %dK, size %dK
6sisfb: Unsupported rate %d for %dx%d
3sisfb: Invalid VESA mode 0x%x'
3sisfb: Invalid mode. Using default.
3sisfb: Setting mode[0x%x] failed
3sisfb: Unknown command 0x%x
6sisfb: Deprecated ioctl call received - update your application!
3sisfb: Unable to map maximum video RAM for size detection
3sisfb: Video RAM size detection limited to %dMB
3sisfb: Unable to detect RAM size. Setting default.
RAM type something else than expected: %d
%s: RAM size detection failed: %d
3sisfb: Please connect power to the card.
7sisfb: Failed to map memory for size detection, assuming 8MB
7sisfb: PCI device is disabled, but marked as boot video device ???
7sisfb: I will not accept this as the primary VGA device
7sisfb: Identified [%s %s] requiring Chrontel/GPIO setup
6sisfb: Video ROM usage disabled
6sisfb: Card is not POSTed and sisfb can't do this either.
6sisfb: Fatal error: Unable to determine VRAM size.
3sisfb: Fatal error: Unable to reserve %dMB framebuffer memory
3sisfb: Is there another framebuffer driver active?
3sisfb: Fatal error: Unable to reserve MMIO region
3sisfb: Fatal error: Unable to map framebuffer memory
3sisfb: Fatal error: Unable to map MMIO region
6sisfb: Video RAM at 0x%lx, mapped to 0x%lx, size %ldk
6sisfb: Viewport offset %ldk
6sisfb: MMIO at 0x%lx, mapped to 0x%lx, size %ldk
4sisfb: Failed to initialize offscreen memory heap
3Mode %dx%dx%d failed validation
6sisfb: WARNING: Refresh rate exceeds monitor specs!
6sisfb: Default mode is %dx%dx%d (%dHz)
7sisfb: Initial vbflags 0x%x
3sisfb: Fatal error: Failed to register framebuffer
6sisfb: 2D acceleration is %s, y-panning %s
6fb%d: %s frame buffer device version %d.%d.%d
6sisfb: Copyright (C) 2001-2005 Thomas Winischhofer
7sisfb: Adapted from %dx%dx%d to %dx%dx%d
3sisfb: Failed to find supported mode near %dx%dx%d
3sisfb: Mode %dx%dx%d not supported
3sisfb: Internal error, using default mode.
3sisfb: Mode 'none' not supported anymore. Using default.
parm=nocrt2rate:
Setting this to 1 will force the driver to use the default refresh rate for
CRT2 if CRT2 type is VGA. (default: 0, use same rate as CRT1)
parm=tvyposoffset:
Relocate TV output vertically. Possible parameters: -32 through 32.
Default: 0
parm=tvxposoffset:
Relocate TV output horizontally. Possible parameters: -32 through 32.
Default: 0
parm=tvstandard:
This allows overriding the BIOS default for the TV standard. Valid choices are
pal, ntsc, palm and paln. (default: [auto; pal or ntsc only])
parm=lvdshl:
Please refer to documentation for more information on this option.
parm=specialtiming:
Please refer to documentation for more information on this option.
parm=pdc1:
This is same as pdc, but for LCD-via CRT1. Hence, this is for the 315/330/340
series only. (default: autodetected if LCD is in LCD-via-CRT1 mode during
startup) - Note: currently, this has no effect because LCD-via-CRT1 is not
implemented yet.
parm=pdc:
This is for manually selecting the LCD panel delay compensation. The driver
should detect this correctly in most cases; however, sometimes this is not
possible. If you see 'small waves' on the LCD, try setting this to 4, 32 or 24
on a 300 series chipset; 6 on other chipsets. If the problem persists, try
other values (on 300 series: between 4 and 60 in steps of 4; otherwise: any
value from 0 to 31). (default: autodetected, if LCD is active during start)
parm=scalelcd:
Setting this to 1 will force the driver to scale the LCD image to the panel's
native resolution. Setting it to 0 will disable scaling; LVDS panels will
show black bars around the image, TMDS panels will probably do the scaling
themselves. Default: 1 on LVDS panels, 0 on TMDS panels
parm=forcecrt2type:
If this option is omitted, the driver autodetects CRT2 output devices, such as
LCD, TV or secondary VGA. With this option, this autodetection can be
overridden. Possible parameters are LCD, TV, VGA or NONE. NONE disables CRT2.
On systems with a SiS video bridge, parameters SVIDEO, COMPOSITE or SCART can
be used instead of TV to override the TV detection. Furthermore, on systems
with a SiS video bridge, SVIDEO+COMPOSITE, HIVISION, YPBPR480I, YPBPR480P,
YPBPR720P and YPBPR1080I are understood. However, whether or not these work
depends on the very hardware in use. (default: [autodetected])
parm=forcecrt1:
Normally, the driver autodetects whether or not CRT1 (external VGA) is
connected. With this option, the detection can be overridden (1=CRT1 ON,
0=CRT1 OFF) (default: [autodetected])
parm=rate:
Selects the desired vertical refresh rate for CRT1 (external VGA) in Hz.
If the mode is specified in the format XxY-Depth@Rate, this parameter
will be ignored (default: 60)
parm=vesa:
Selects the desired default display mode by VESA defined mode number, eg.
0x117 (default: 0x0103)
parm=mode:
Selects the desired default display mode in the format XxYxDepth,
eg. 1024x768x16. Other formats supported include XxY-Depth and
XxY-Depth@Rate. If the parameter is only one (decimal or hexadecimal)
number, it will be interpreted as a VESA mode number. (default: 800x600x8)
parm=nomax:
If y-panning is enabled, sisfb will by default use the entire available video
memory for the virtual screen in order to optimize scrolling performance. If
this is set to anything other than 0, sisfb will not do this and thereby
enable the user to positively specify a virtual Y size of the screen using
fbset. (default: 0)
parm=noypan:
If set to anything other than 0, y-panning will be disabled and scrolling
will be performed by redrawing the screen. (default: 0)
parm=noaccel:
If set to anything other than 0, 2D acceleration will be disabled.
(default: 0)
parm=mem:
Determines the beginning of the video memory heap in KB. This heap is used
for video RAM management for eg. DRM/DRI. On 300 series, the default depends
on the amount of video RAM available. If 8MB of video RAM or less is available,
the heap starts at 4096KB, if between 8 and 16MB are available at 8192KB,
otherwise at 12288KB. On 315/330/340 series, the heap size is 32KB by default.
The value is to be specified without 'KB'.
parmtype=nocrt2rate:int parmtype=tvyposoffset:int parmtype=tvxposoffset:int parmtype=tvstandard:charp parmtype=lvdshl:int parmtype=specialtiming:charp parmtype=pdc1:int parmtype=pdc:int parmtype=scalelcd:int parmtype=forcecrt2type:charp parmtype=forcecrt1:int parmtype=rate:int parmtype=vesa:int parmtype=mode:charp parmtype=useoem:int parmtype=userom:int parmtype=nomax:int parmtype=noypan:int parmtype=noaccel:int parmtype=mem:int author=Thomas Winischhofer <thomas@winischhofer.net>, Others license=GPL description=SiS 300/540/630/730/315/55x/65x/661/74x/330/76x/34x, XGI V3XT/V5/V8/Z7 framebuffer device driver srcversion=DFEB2BDF1E8E56864209A11 alias=pci:v000018CAd00000040sv*sd*bc*sc*i* alias=pci:v000018CAd00000020sv*sd*bc*sc*i* alias=pci:v00001039d00006330sv*sd*bc*sc*i* alias=pci:v00001039d00000330sv*sd*bc*sc*i* alias=pci:v00001039d00006325sv*sd*bc*sc*i* alias=pci:v00001039d00005315sv*sd*bc*sc*i* alias=pci:v00001039d00000325sv*sd*bc*sc*i* alias=pci:v00001039d00000315sv*sd*bc*sc*i* alias=pci:v00001039d00000310sv*sd*bc*sc*i* alias=pci:v00001039d00006300sv*sd*bc*sc*i* alias=pci:v00001039d00005300sv*sd*bc*sc*i* alias=pci:v00001039d00000300sv*sd*bc*sc*i* depends= intree=Y vermagic=3.11.0-15-generic SMP mod_unload modversions sis_free_new sis_malloc_new sis_free sis_malloc -#w module_layout __request_region Yc kmalloc_caches 8.G< pci_bus_read_config_byte h vmalloc ,i param_ops_int Xi iomem_resource SMu strlen _@ framebuffer_release T pci_unmap_rom jo dev_set_drvdata X( pci_get_slot E pci_disable_device @!r mtrr_add ) simple_strtoul )g __get_user_4 PH pci_get_class DX= strnicmp ѱ cfb_fillrect _ ܉ mutex_unlock vfree Sq sprintf ]O _copy_to_user r5 param_ops_charp ŏW memset t cfb_imageblit 1m dev_err I' printk Z sscanf Ȑ fb_alloc_cmap \ pci_map_rom . < register_framebuffer f strncpy Z strncmp HW strlcpy d pci_bus_write_config_dword : mutex_lock capable D _dev_info \ __put_user_4 5B ioremap_nocache : pci_bus_read_config_word M pci_bus_read_config_dword __stack_chk_fail m __fentry__ 4a| __release_region $ pci_unregister_driver kmem_cache_alloc_trace fus framebuffer_alloc pci_bus_write_config_byte 8߬i memcpy S9 iounmap N9-' mtrr_del __pci_register_driver (u pci_get_device > dev_warn 6 cfb_copyarea pci_dev_put Q pci_enable_device @kO _copy_from_user dev_get_drvdata strcpy 1L: unregister_framebuffer 9 9 S 9 c 9 9 9 % 9 S 9 %c 9 0 9 0c
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; ) #; *; :; H; V; o 0 f; P u; ; $c ; m ; @ ) ; ; 1 ; e70 ; <JE ; ? < ` (< .< M >< K< X< a< L x< s < L < < < ) < < < q = W = (= . 6= H= p q Z= g= w= 0 = , = = i = = = = = P. ; = = > > $> 2 9> R> a> r> P` > / > ` 1 sisfb_open sisfb_release sisfb_getheapsize sisfb_poh_free sisfb_heap sisfb_interpret_edid sisfb_ddcsmodes sisfb_ddcfmodes sisfb_remove sisfb_detect_VB_connect sisfb_save_pdc_emi sisfb_set_TVyposoffset sisfb_set_TVxposoffset sisfb_detect_lcd_type sis300paneltype sis661paneltype sis310paneltype sisfb_fstn sis_lcd_data sisfb_engine_init sisfb_post_xgi_ramtype sisfb_setcolreg sisfb_detect_custom_timing mycustomttable sisfb_get_dram_size SiS_SenseLCD sisfb_handle_ddc SISDoSense SiS_Sense30x SiS_SenseCh sisfb_get_VB_type sisfb_validate_mode sisbios_mode sisfb_search_crt2type sis_crt2type sisfb_crt2type sisfb_tvplug sisfb_crt2flags sisfb_dstn sisfb_search_specialtiming sisfb_specialtiming sisfb_bpp_to_var.isra.4 sisfb_poh_new_node.isra.6 sisfb_poh_allocate sis_int_malloc sisfb_heap_init sisfb_check_rom.isra.10.part.11 sisfb_find_rom sisfb_search_refresh_rate.isra.13 sisfb_vrate sisfb_set_vparms sisfb_search_vesamode.part.15 sisfb_mode_idx sisfb_search_vesamode sisfb_bridgeisslave sisfb_set_pitch sisfb_myblank sisfb_blank sisfballowretracecrt1.isra.17 sisfb_setupvbblankflags sisfb_CheckVBRetrace sisfb_sense_crt1 sisfb_post_xgi_delay.isra.20 sisfb_post_xgi_setclocks.isra.21 sisfb_post_xgi_ddr2_mrs_xg21 sisfb_post_xgi_ddr2_mrs_default.isra.22 sisfb_post_xgi_ddr2 cs168.32624 cs160.32623 cs158.32622 sisfb_post_xgi_rwtest sisfb_set_base_CRT1 sisfb_set_base_CRT2 sisfb_pan_display sisfb_check_engine_and_sync sisfb_pre_setmode sisfb_post_setmode sisfb_post_300_buswidth.isra.29 sisfb_post_300_rwtest.isra.30 SiS_DRAMType sisfb_set_mode.isra.31 sisfb_handle_command sisfb_ioctl sisfb_get_fix.isra.33 sisfb_find_host_bridge.isra.36 sisfb_post_map_vram.isra.39.part.40 sisfb_post_xgi_ramsize dramsr13_4.32589 dramsr13.32588 sisfb_post_xgi cs78.32658 cs76.32659 cs7b.32660 cs128.32664 cs33a.32667 cs31a.32666 cs148.32665 cs45a.32668 cs170.32669 cs1a8.32670 cs100.32671 cs158.32661 cs160.32662 cs168.32663 __func__.32729 sisfb_post_sis300 sisfb_verify_rate.part.43 sisfb_verify_rate sisfb_probe sisfb_off card_list sisfb_chip_info sisfb_parm_mem sisfb_parm_rate sisfb_accel sisfb_ypan sisfb_max sisfb_userom sisfb_useoem sisfb_crt1off sisfb_forcecrt1 sisfb_tvstd sisfb_tvxposoffset sisfb_tvyposoffset sisfb_nocrt2rate sisfb_scalelcd sisfb_lvdshl my_default_var sisfb_pdc nbridgeids.32079 sisfb_pdca mychswtable sisfb_ops sisfb_check_var sisfb_do_set_var.isra.41.constprop.45 sisfb_set_par sisfb_search_mode.constprop.46 sisfb_init_module rate scalelcd forcecrt2type tvstandard sis_tvtype mode vesa forcecrt1 noaccel noypan nomax mem userom useoem pdc pdc1 specialtiming nocrt2rate lvdshl tvxposoffset sisfb_driver tvyposoffset sisfb_remove_module __ksymtab_sis_free_new __kstrtab_sis_free_new __kcrctab_sis_free_new __ksymtab_sis_malloc_new __kstrtab_sis_malloc_new __kcrctab_sis_malloc_new __ksymtab_sis_free __kstrtab_sis_free __kcrctab_sis_free __ksymtab_sis_malloc __kstrtab_sis_malloc __kcrctab_sis_malloc __UNIQUE_ID_nocrt2rate40 __UNIQUE_ID_tvyposoffset39 __UNIQUE_ID_tvxposoffset38 __UNIQUE_ID_tvstandard37 __UNIQUE_ID_lvdshl36 __UNIQUE_ID_specialtiming35 __UNIQUE_ID_pdc134 __UNIQUE_ID_pdc33 __UNIQUE_ID_scalelcd32 __UNIQUE_ID_forcecrt2type31 __UNIQUE_ID_forcecrt130 __UNIQUE_ID_rate29 __UNIQUE_ID_vesa28 __UNIQUE_ID_mode27 __UNIQUE_ID_nomax26 __UNIQUE_ID_noypan25 __UNIQUE_ID_noaccel24 __UNIQUE_ID_mem23 __UNIQUE_ID_nocrt2ratetype22 __param_nocrt2rate __param_str_nocrt2rate __UNIQUE_ID_tvyposoffsettype21 __param_tvyposoffset __param_str_tvyposoffset __UNIQUE_ID_tvxposoffsettype20 __param_tvxposoffset __param_str_tvxposoffset __UNIQUE_ID_tvstandardtype19 __param_tvstandard __param_str_tvstandard __UNIQUE_ID_lvdshltype18 __param_lvdshl __param_str_lvdshl __UNIQUE_ID_specialtimingtype17 __param_specialtiming __param_str_specialtiming __UNIQUE_ID_pdc1type16 __param_pdc1 __param_str_pdc1 __UNIQUE_ID_pdctype15 __param_pdc __param_str_pdc __UNIQUE_ID_scalelcdtype14 __param_scalelcd __param_str_scalelcd __UNIQUE_ID_forcecrt2typetype13 __param_forcecrt2type __param_str_forcecrt2type __UNIQUE_ID_forcecrt1type12 __param_forcecrt1 __param_str_forcecrt1 __UNIQUE_ID_ratetype11 __param_rate __param_str_rate __UNIQUE_ID_vesatype10 __param_vesa __param_str_vesa __UNIQUE_ID_modetype9 __param_mode __param_str_mode __UNIQUE_ID_useoemtype8 __param_useoem __param_str_useoem __UNIQUE_ID_useromtype7 __param_userom __param_str_userom __UNIQUE_ID_nomaxtype6 __param_nomax __param_str_nomax __UNIQUE_ID_noypantype5 __param_noypan __param_str_noypan __UNIQUE_ID_noacceltype4 __param_noaccel __param_str_noaccel __UNIQUE_ID_memtype3 __param_mem __param_str_mem __UNIQUE_ID_author2 __UNIQUE_ID_license1 __UNIQUE_ID_description0 sisfb_pci_table SiS300SubsequentScreenToScreenCopy SiS300SetupForSolidFill sisPatALUConv SiS300SubsequentSolidFillRect SiS310SubsequentScreenToScreenCopy SiS310SetupForSolidFill SiS310SubsequentSolidFillRect SiS310SetupForScreenToScreenCopy.constprop.3 SiS300SetupForScreenToScreenCopy.constprop.4 myrops InitCommonPointer SiS_ExtNTSCData SiS_StNTSCData SiS_SModeIDTable SiS_StResInfo SiS_ModeResInfo SiS_StandTable SiS_NTSCTiming SiS_PALTiming SiS_HiTVSt1Timing SiS_HiTVSt2Timing SiS_HiTVExtTiming SiS_HiTVGroup3Data SiS_HiTVGroup3Simu SiS_StPALData SiS_ExtPALData SiS_StHiTVData SiS_St2HiTVData SiS_ExtHiTVData SiS_St525pData SiS_St750pData SiS_Ext750pData SiS_OutputSelect SiS_SoftSetting SiS_LCD1280x720Data SiS_StLCD1280x768_2Data SiS_ExtLCD1280x768_2Data SiS_LCD1280x800Data SiS_LCD1280x800_2Data SiS_LCD1280x854Data SiS_LCD1280x960Data SiS_StLCD1400x1050Data SiS_ExtLCD1400x1050Data SiS_LCD1680x1050Data SiS_StLCD1600x1200Data SiS_ExtLCD1600x1200Data SiS_NoScaleData SiS_LVDS320x240Data_1 SiS_LVDS320x240Data_2 SiS_LVDS640x480Data_1 SiS_LVDS800x600Data_1 SiS_LVDS1024x600Data_1 SiS_LVDS1024x768Data_1 SiS_LVDSCRT1320x240_1 SiS_LVDSCRT1320x240_2 SiS_LVDSCRT1320x240_2_H SiS_LVDSCRT1320x240_3 SiS_LVDSCRT1320x240_3_H SiS_LVDSCRT1640x480_1 SiS_LVDSCRT1640x480_1_H SiS_CHTVUNTSCData SiS_CHTVONTSCData InitTo300Pointer SiS300_MCLKData_300 SiS300_MCLKData_630 SiS300_VBModeIDTable SiS300_EModeIDTable SiS300_RefIndex SiS300_CRT1Table SiS300_VCLKData SiS300_SR15 SiS300_PanelDelayTbl SiS300_ExtLCD1024x768Data SiS300_St2LCD1024x768Data SiS300_ExtLCD1280x1024Data SiS300_St2LCD1280x1024Data SiS300_CRT2Part2_1024x768_1 SiS300_CRT2Part2_1024x768_2 SiS300_CRT2Part2_1024x768_3 SiS300_CHTVUPALData SiS300_CHTVOPALData SiS300_CHTVSOPALData SiS300_LVDS848x480Data_1 SiS300_LVDS848x480Data_2 SiS300_LVDSBARCO1024Data_1 SiS300_LVDSBARCO1366Data_1 SiS300_LVDSBARCO1366Data_2 SiS300_PanelType04_1a SiS300_PanelType04_2a SiS300_PanelType04_1b SiS300_PanelType04_2b SiS300_CHTVCRT1UNTSC SiS300_CHTVCRT1ONTSC SiS300_CHTVCRT1UPAL SiS300_CHTVCRT1OPAL SiS300_CHTVCRT1SOPAL SiS300_CHTVReg_UNTSC SiS300_CHTVReg_ONTSC SiS300_CHTVReg_UPAL SiS300_CHTVReg_OPAL SiS300_CHTVReg_SOPAL SiS300_CHTVVCLKUNTSC SiS300_CHTVVCLKONTSC SiS300_CHTVVCLKUPAL SiS300_CHTVVCLKOPAL SiS300_CHTVVCLKSOPAL InitTo310Pointer SiS310_EModeIDTable SiS310_RefIndex SiS310_CRT1Table SiS310_MCLKData_0_340 SiS310_MCLKData_1_340 SiS310_VCLKData SiS310_VBVCLKData SiS310_SR15 SiS310_PanelDelayTbl SiS310_PanelDelayTblLVDS SiS310_St2LCD1024x768Data SiS310_ExtLCD1024x768Data SiS310_St2LCD1280x1024Data SiS310_ExtLCD1280x1024Data SiS310_CRT2Part2_1024x768_1 SiS310_CHTVUPALData SiS310_CHTVOPALData SiS310_CHTVUPALMData SiS310_CHTVOPALMData SiS310_CHTVUPALNData SiS310_CHTVOPALNData SiS310_CHTVSOPALData SiS310_CHTVCRT1UNTSC SiS310_CHTVCRT1ONTSC SiS310_CHTVCRT1UPAL SiS310_CHTVCRT1OPAL SiS310_CHTVReg_UNTSC SiS310_CHTVReg_ONTSC SiS310_CHTVReg_UPAL SiS310_CHTVReg_OPAL SiS310_CHTVReg_UPALM SiS310_CHTVReg_OPALM SiS310_CHTVReg_UPALN SiS310_CHTVReg_OPALN SiS310_CHTVVCLKUNTSC SiS310_CHTVVCLKONTSC SiS310_CHTVVCLKUPAL SiS310_CHTVVCLKOPAL SiS310_CHTVVCLKUPALM SiS310_CHTVVCLKOPALM SiS310_CHTVVCLKUPALN SiS310_CHTVVCLKOPALN SiS310_MCLKData_0_761 SiS310_MCLKData_1 SiS310_MCLKData_0_660 SiS310_MCLKData_0_760 SiS310_MCLKData_0_650 SiS310_MCLKData_0_315 SiS310_MCLKData_0_330 SiS_GetSysFlags SiS_GetVBType SiS_OpenCRTC SiS_SetSeqRegs SiS_SetCRTCRegs SiS_SetATTRegs SiS_ResetCRT1VCLK SiS_ResetVB SiS_StrangeStuff SiSSetLVDSetc SiS_SetVCLKState SiS_ClearBuffer SiS_Handle760 SiS_Get310DRAMType SiS_GetMCLK SiSInitPCIetc.isra.9 SiS_DoLowModeTest.isra.10 SiS_GetModeID.isra.0.constprop.14 ModeIndex_856x480 ModeIndex_300_1360x1024 ModeIndex_640x400 ModeIndex_1680x1050 ModeIndex_800x480 ModeIndex_1400x1050 ModeIndex_1152x768 ModeIndex_720x576 ModeIndex_960x600 ModeIndex_768x576 ModeIndex_320x240 ModeIndex_1024x600 ModeIndex_1600x1200 ModeIndex_1152x864 ModeIndex_800x600 ModeIndex_720x480 ModeIndex_310_2048x1536 ModeIndex_1920x1080 ModeIndex_848x480 ModeIndex_310_1280x768 ModeIndex_512x384 ModeIndex_400x300 ModeIndex_1280x854 ModeIndex_1360x768 ModeIndex_1920x1440 ModeIndex_1024x576 ModeIndex_640x480 ModeIndex_320x200 ModeIndex_1024x768 ModeIndex_1280x800 ModeIndex_1280x720 ModeIndex_1280x1024 ModeIndex_1280x960 ModeIndex_960x540 ModeIndex_300_2048x1536 ModeIndex_300_1280x768 SiS_SetSegmentReg.constprop.15 ModeIndex_320x240_FSTN SiS_SetCRT1VCLK SiS_SetCRT1FIFO_310 SiSDetermineROMUsage SiS_SetCRT1FIFO_630 FQBQData730.29698 FQBQData.29697 colortharray.29699 LatencyFactor.29676 LatencyFactor730.29677 SiS_SetCRT1CRTC ColorDepth.29508 SiS_SetCRT1Offset SiS_SetCRT1ModeRegs ThTiming.29630 SiS_DoCalcDelay ThLowA.29635 ThLowB.29640 SiS_SetCRT1FIFO_300 colortharray.29670 SiS_MDA_DAC SiS_CGA_DAC SiS_EGA_DAC SiS_VGA_DAC SiS_SetCRT1Group SiS_GetCRT2Ptr CSWTCH.53 SiS_GetLVDSDesData SiS_GetCRT2Part2Ptr SiS_GetLVDSCRT1Ptr GetOEMTVPtr661_2_OLD SiS_CRT2IsLCD GetLCDStructPtr661 SiS_LCDStruct661 SiS_GetLCDInfoBIOS GetLCDStructPtr661_2 SiS_CR36BIOSWord23d SiS_CR36BIOSWord23b SiS_HaveBridge SiS_SetCRT2FIFO_310 SiS_SetTVSpecial SiS_Group2LCDSpecial atable.29896 SiS_SetGroup2_Tail SiS_Set300Part2Regs SiS_HandlePWD SetOEMLCDData2 barco_p1 SiS_FinalizeLCD SetPanelParms661 SiS_GetRAMDAC2DATA SiS_SetGroup1_301 CRTranslation.29760 SiS_SetCRT2Sync SiS_AdjustCRT2Rate.isra.0 SiS_CheckScaling SiS_CalcPanelLinkTiming.part.3 SiS_GetGroup2CLVXPtr.isra.5 SiS_Part2CLVX_1 SiS_Part2CLVX_2 SiS_Part2CLVX_3 SiS_Part2CLVX_4 SiS_Part2CLVX_6 SiS_Part2CLVX_5 SiS_SetupDDCN GetTVPtrIndex.isra.10 SetPhaseIncr SiS310_TVPhaseIncr2 SiS310_TVPhaseIncr1 SiS_TVPhase SetYFilter SiS310_TVYFilter2 SiS310_TVYFilter1 GetOEMTVPtr661.isra.12 SetAntiFlicker SiS310_TVAntiFlick1 SetEdgeEnhance SiS310_TVEdge1 GetOEMTVPtr.isra.14 SiS_WaitRetrace2.isra.17 SiS_IsNotM650orLater.isra.18 GetLCDPtrIndexBIOS SiS_LCDAEnabled.isra.19 SiS_BridgeInSlavemode.isra.21 SiS_IsTVOrYPbPrOrScart.isra.22 SiS_IsLCDOrLCDA.isra.25 SiS_WeHaveBacklightCtrl.isra.26 SetOEMTVDelay.isra.29 SiS300_OEMTVDelay301 SiS300_OEMTVDelayLVDS SetOEMAntiFlicker.isra.30 SiS300_OEMTVFlicker SiS_SetRegSR11ANDOR.isra.31 SiS_SetGroup2_C_ELV.isra.33 SiS_SetGroup3.isra.34 SiS_HiTVGroup3_1 SiS_HiTVGroup3_2 SetOEMPhaseIncr.isra.35 SiS300_Phase2 SiS300_Phase1 SetOEMYFilter.isra.36 SiS300_Filter2 SiS300_Filter1 SiS_SetGroup4_C_ELV.isra.38 SetDelayComp.isra.39 SiS310_TVDelayCompensation_301 SiS310_TVDelayCompensation_301B SiS310_TVDelayCompensation_LVDS SiS310_LCDDelayCompensation_301 SiS310_LCDDelayCompensation_3xx301LV SiS310_TVDelayCompensation_740301B SiS310_TVDelayCompensation_651301LV SiS310_TVDelayCompensation_651302LV SiS310_LCDDelayCompensation_650301LV SiS310_LCDDelayCompensation_3xx301B SiS310_LCDDelayCompensation_651301LV SiS310_LCDDelayCompensation_651302LV SiS_ModCRT1CRTC.part.42 CRIdx.30061 SiS_ModCRT1CRTC SetCRT2SyncDither661.part.43 SiS_GetRatePtr.part.46 LCDRefreshIndex.29075 SiS_GetCRT2ResInfo.part.57 SiS_GetCRT2Data301 SiS310_ExtCompaq1280x1024Data SiS_GetCRT2DataLVDS SiS_InitDDCRegs.isra.16.constprop.62 GetOEMLCDPtr.constprop.64 SetOEMLCDDelay.isra.28 SiS300_OEMLCDDelay2 SiS300_OEMLCDDelay4 SiS300_OEMLCDDelay3 SiS300_OEMLCDDelay5 SiS_OEM300Setting.isra.37 SiS_SetSCLKHigh SiS_SetSCLKLow SiS_SetStart SiS_WriteDDC2Data SiS_WriteDABDDC SiS_PrepareDDC SiS_ReadDDC2Data SiS_SendACK SiS_SetStop SiS_GetChReg SiS_SetChReg SiS_SetTrumpBlockLoop SiS_GenericDelay SiS_LongDelay SiS_PanelDelay SiS_PanelDelayLoop.constprop.63 SiS_SetSwitchDDC2 SiS_DoProbeDDC SiS_ReadDDC SiS_SetTrumpionBlock SiS_SetGroup1_LVDS SiS300_TrumpionData SiS_WaitVBRetrace SiS_VBLongWait SiS_IsDualLink SiS_SetCRT2ModeRegs SiS_SetGroup2 SiS_YPbPrTable SiS310_CRT2Part2_Asus1024x768_3 SiS_SetDualLinkEtc SiS_IsVAorLCD SiS300SeriesLCDRes.29309 nonscalingmodes.29381 nonscalingmodes.29376 nonscalingmodes.29374 nonscalingmodes.29372 nonscalingmodes.29353 nonscalingmodes.29383 nonscalingmodes.29359 nonscalingmodes.29366 nonscalingmodes.29361 nonscalingmodes.29355 nonscalingmodes.29351 nonscalingmodes.29349 SiS_SetCRT2FIFO_300 colortharray.29739 SiS_SetGroup1 SiS_SetCRT2VCLK SiS_SetGroup4 SiS_SetCRT2ECLK SetDelayComp661 SiS_OEM310Setting SiS_OEM661Setting SiS_ChrontelPowerSequencing table1400_650.30130 regtable.30124 asus1400_740.30128 table1400_740.30126 table1024_650.30129 asus1024_740.30127 table1024_740.30125 SiS_SetCH701xForLCD table1600_650.30150 table1400_740.30145 regtable.30142 table1600_740.30146 table1024_650.30147 table1280_650.30148 table1280_740.30144 table1400_650.30149 table1024_740.30143 SiS_ChrontelResetVSync SiS_Chrontel701xOn SiS_ChrontelResetDB.part.59 SiS_ChrontelResetDB SiS_ChrontelDoSomething2 SiS_ChrontelDoSomething3 SiS_ChrontelDoSomething1 SiS_ChrontelInitTVVSync SiS_EnableBridge SiS_SetCHTVReg __UNIQUE_ID_srcversion14 __UNIQUE_ID_alias13 __UNIQUE_ID_alias12 __UNIQUE_ID_alias11 __UNIQUE_ID_alias10 __UNIQUE_ID_alias9 __UNIQUE_ID_alias8 __UNIQUE_ID_alias7 __UNIQUE_ID_alias6 __UNIQUE_ID_alias5 __UNIQUE_ID_alias4 __UNIQUE_ID_alias3 __UNIQUE_ID_alias2 __module_depends ____versions __UNIQUE_ID_intree1 __UNIQUE_ID_vermagic0 unregister_framebuffer SiS_WaitRetrace1 strcpy SiS_GetModeID_LCD SiSSetMode dev_get_drvdata SiS_GetVBInfo SiS_DisplayOff sisfb_initaccel _copy_from_user fbcon_sis_sync pci_enable_device SiS_GetCH701x __this_module sisfb_read_nbridge_pci_dword SiS_GetCH700x pci_dev_put cfb_copyarea SiS_GetModeID_VGA2 dev_warn pci_get_device fbcon_sis_copyarea SiS_SetReg SiS_SetChrontelGPIO SiS_SetCH701x __pci_register_driver sis_malloc mtrr_del iounmap cleanup_module SiS_Chrontel701xBLOff memcpy SiSDetermineROMLayout661 SiS_GetRefCRT1CRTC sisfb_mode_rate_to_ddata SiS_GetModeFlag SiSInitPtr sis_free SiS_IsDualEdge pci_bus_write_config_byte framebuffer_alloc SiS_SetCRT2Group SiS_GetOffset SiS_DDC2Delay SiS_GetRefCRTVCLK kmem_cache_alloc_trace SiS_GetResInfo pci_unregister_driver __release_region __fentry__ init_module SiS_Generic_ConvertCRData sisfb_mode_rate_to_dclock SiS_UnLockCRT2 fbcon_sis_fillrect SiS_LoadDAC __stack_chk_fail SiS_SetRegOR SiS_SetEnableDstn pci_bus_read_config_dword SiS_GetReg pci_bus_read_config_word ioremap_nocache __put_user_4 SiS_SiS30xBLOn _dev_info capable SiS_GetModeID_TV SiSRegInit SiS_DisableBridge SiS_IsVAMode __mod_pci_device_table sisfb_read_mio_pci_word SiS_GetRatePtr SiS_GetRegShort mutex_lock pci_bus_write_config_dword strlcpy strncmp sisfb_write_nbridge_pci_dword strncpy register_framebuffer pci_map_rom SiS_SetRegLong fb_alloc_cmap sscanf printk dev_err sisfb_syncaccel cfb_imageblit SiS_SetRegByte SiS_GetModePtr SiS_GetFIFOThresholdB300 memset param_ops_charp _copy_to_user SiS_SetTVMode SiS_ReadDDC1Bit SiS_GetRegLong SiS_CalcCRRegisters __crc_sis_free_new SiS_HandleDDC sisfb_write_nbridge_pci_byte sprintf SiS_DisplayOn __crc_sis_malloc __crc_sis_free sisfb_read_lpc_pci_dword SiS_GetLCDResInfo vfree SiS_GetVCLK2Ptr mutex_unlock cfb_fillrect strnicmp SiS_CalcLCDACRT1Timing sisfb_gettotalfrommode SiS_SearchModeID pci_get_class __get_user_4 SiS_GetLatencyFactor630 simple_strtoul mtrr_add SiS_GetFIFOThresholdIndex300 sis_free_new pci_disable_device SiS_SetCH700x SiS_SetEnableFstn SiS_GetColorDepth pci_get_slot SiS_SetRegShort SiS_GetRegByte SiS_SetRegAND SiS_Chrontel701xBLOn dev_set_drvdata pci_unmap_rom SiS_SetYPbPr framebuffer_release SiS_SiS30xBLOff strlen iomem_resource param_ops_int vmalloc __crc_sis_malloc_new pci_bus_read_config_byte kmalloc_caches __request_region SiS_SetCH70xxANDOR sis_malloc_new SiS_SetRegANDOR ! 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