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i2c read error on %d remove slave fe %p (index %i) no frontend to be removed set slave fe %p to index %i too many slave frontend wrong Device ID (%x) found DiB8000A found DiB8000B found DiB8000C found DiB8096P wrong Vendor ID (read=0x%x) TMCC lock on the slave%i dib8000_autosearch_irq failed AGC split_offset: %d init sdram Enable Mpeg mux SET DIBSTREAM TX ON HOST BUS SET MPEG MUX ON HOST BUS could not start Slow ADC ifreq: %d %x, inversion: %d clk_cfg1: 0x%04x Index %x, PID %d, OnOff %d pid filter enabled %d sleep dib8096p: %d gpio dir: %x: gpio val: %x Old Internal = %d New Internal = %d Waiting for PLL to lock set diversity input to %i using default timf using updated timf acquisition mode activated Configure DibStream Tx SET MPEG ON DIBSTREAM TX SET DIV_OUT ON DIBSTREAM TX SET ADC_OUT ON DIBSTREAM TX autosearch succeeded on fe%i tuning done with status %d TunerITF: read busy (empty) dib8000_attach &state->i2c_buffer_lock %s: not enough memory client.i2c_buffer_lock #%d: not identified sub_channel_prbs_group = %d , subchannel =%d prbs = 0x%04x dib8000_get_frontend GI = 1/32 dib8000_get_frontend GI = 1/16 dib8000_get_frontend GI = 1/8 dib8000_get_frontend GI = 1/4 dib8000_get_frontend : partial_reception = %d dib8000_get_frontend : Layer %d segments = %d dib8000_get_frontend : Layer %d time_intlv = %d dib8000_get_frontend : Layer %d Code Rate = 1/2 dib8000_get_frontend : Layer %d Code Rate = 2/3 dib8000_get_frontend : Layer %d Code Rate = 3/4 dib8000_get_frontend : Layer %d Code Rate = 5/6 dib8000_get_frontend : Layer %d Code Rate = 7/8 dib8000_get_frontend : Layer %d DQPSK dib8000_get_frontend : Layer %d QPSK dib8000_get_frontend : Layer %d QAM16 dib8000_get_frontend : Layer %d QAM64 dib8000_autosearch_irq: max correlation result available dib8000_autosearch_irq succeeded powermode : 774 : %x ; 775 : %x; 776 : %x ; 900 : %x; 1280 : %x no valid AGC configuration found for band 0x%02x WBD: ref: %d, sel: %d, active: %d, alpha: %d setting a DDS frequency offset of %c%dkHz %dkhz tuner offset (frequency = %dHz & current_rf = %dHz) total_dds_offset_hz = %d SET DEM OUT OLD INTERF ON HOST BUS Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d) Xtal = %d , New Fmem = %d New Fdemod = %d, New Fsampling = %d PLL Updated with prediv = %d and loopdiv = %d PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d) PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d) PLL: Update ratio (prediv: %d, ratio: %d) Updated timing frequency: %d (default: %d) Using list for autosearch : %d layer%i: time interleaver = %d Deeper interleaver mode = %d on layer %d : timeout mult factor = %d => will use timeout = %d Mpeg locks [ L0 : %d | L1 : %d | L2 : %d ] -I- Setting output mode for demod %p to %d Unhandled output_mode passed to be set for demod %p error : dib8000 MA not supported using standard PAD-drive-settings, please adjust settings in config-struct to be optimal. OUTPUT_MODE could not be resetted. Tuner ITF: write busy (overflow) dib8096P setting output mode TS_SERIAL using Mpeg Mux dib8096P setting output mode TS_PARALLEL_GATED using Mpeg Mux dib8096P setting output mode TS_PARALLEL_CONT using Smooth block dib8096P setting output mode TS_FIFO using Smooth block dib8096P setting output mode MODE_DIVERSITY dib8096P setting output mode MODE_ANALOG_ADC output_mpeg2_in_188_bytes = %d Configure DibStream Rx synchroMode = %d %s mode OFF : by default Enable Mpeg INPUT %s ON : Enable diversity INPUT dib8000: must at least specify frequency dib8000: no bandwidth specified, set to default strange callback time something went wrong TunerITF: read busy (overflow) IC %d initialized (to i2c_address 0x%x) [ L G } dib8000_i2c_enumeration DiBcom 8000 ISDB-T 3P/3$ .@ dib8096p_set_diversity_in e ? @
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` f} P ` ! * <l K Q 2;o+ m v hg * 0Q P c(r - #h I Z:R a S w ? lWV ? ! * o3} H 0 _ P | E 3 \ӻ FJK ! 1 9 F = ^ qѕ w Q, 0> p $ " z 2 < E zN _ f B5~ ] dib8096p_i2c_func dib8000_fe_get_tune_settings dib8000_release dib8000_i2c_read16 debug dib8000_i2c_write16 dib8000_get_init_prbs.isra.5 lut_prbs_2k lut_prbs_8k lut_prbs_4k dib8000_identify.part.10 dib8000_identify dib8000_read_word.part.11 dib8000_read_word dib8000_read_unc_blocks dib8000_read_signal_strength dib8000_read_ber dib8000_get_frontend dib8000_read32 lut_1000ln_mant dib8000_get_snr.isra.12 dib8000_read_snr dib8000_read_lock.isra.13 dib8000_read_status dib8000_autosearch_irq.isra.14 dib8000_write_word dib8000_set_adc_state dib8000_set_power_mode dib8000_set_agc_config dib8000_restart_agc dib8000_agc_soft_split dib8000_agc_startup dib8090p_init_sdram dib8000_set_dds dib8000_set_frequency_offset dib8000_wait_lock dib8000_set_layer CSWTCH.180 CSWTCH.182 dib8000_set_sb_channel coff_thres_1seg coff_thres_3seg dib8000_small_fine_tune coeff_8k_sb_3seg_1dqpsk coeff_8k_sb_3seg coeff_4k_sb_3seg_1dqpsk coeff_4k_sb_3seg coeff_2k_sb_3seg_1dqpsk coeff_2k_sb_3seg coeff_4k_sb_1seg_dqpsk coeff_4k_sb_1seg coeff_2k_sb_1seg_dqpsk coeff_2k_sb_1seg coeff_8k_sb_1seg_dqpsk coeff_8k_sb_1seg coeff_4k_sb_3seg_0dqpsk_1dqpsk coeff_4k_sb_3seg_0dqpsk coeff_8k_sb_3seg_0dqpsk_1dqpsk coeff_8k_sb_3seg_0dqpsk coeff_2k_sb_3seg_0dqpsk_1dqpsk coeff_2k_sb_3seg_0dqpsk dib8000_viterbi_state dib8000_set_isdbt_loop_params dib8000_set_subchannel_prbs dib8096p_enMpegMux dib8096p_configMpegMux dib8096p_setHostBusMux dib8000_sad_calib dib8000_wakeup dib8000_reset_pll_common dib8000_reset_pll dib8000_cfg_gpio dib8000_set_diversity_in.isra.17 dib8000_set_bandwidth.isra.19 dib8000_load_ana_fe_coefs.part.20 dib8000_set_13seg_channel ana_fe_coeff_13seg dib8000_set_isdbt_common_channel CSWTCH.161 permu_seg adp_Qdefault CSWTCH.184 CSWTCH.185 adc_target_16dB ana_fe_coeff_1seg ana_fe_coeff_3seg dib8000_update_timf dib8000_autosearch_start.isra.22 dib8000_tune CSWTCH.165 LUT_isdbt_symbol_duration CSWTCH.187 dib8000_set_output_mode.isra.23 dib8000_sleep dib8000_reset dib8000_defaults dib8096p_tuner_write_serpar.isra.16.constprop.25 dib8096p_host_bus_drive.constprop.27 dib8096p_cfg_DibTx.constprop.28 dib8096p_setDibTxMux dib8096p_set_output_mode.isra.24 dib8096p_cfg_DibRx.constprop.29 dib8096p_set_diversity_in.isra.18 __func__.24522 dib8000_set_frontend dib8096p_tuner_read_serpar.constprop.30 dib8096p_tuner_rw_serpar dib8096p_tuner_xfer __key.25341 dib8000_ops dib8096p_tuner_xfer_algo __key.25259 __func__.25256 __UNIQUE_ID_license4 __UNIQUE_ID_description3 __UNIQUE_ID_author2 __ksymtab_dib8000_attach __kstrtab_dib8000_attach __kcrctab_dib8000_attach __ksymtab_dib8000_pid_filter __kstrtab_dib8000_pid_filter __kcrctab_dib8000_pid_filter __ksymtab_dib8000_pid_filter_ctrl __kstrtab_dib8000_pid_filter_ctrl __kcrctab_dib8000_pid_filter_ctrl __ksymtab_dib8000_get_i2c_master __kstrtab_dib8000_get_i2c_master __kcrctab_dib8000_get_i2c_master __ksymtab_dib8000_i2c_enumeration __kstrtab_dib8000_i2c_enumeration __kcrctab_dib8000_i2c_enumeration __ksymtab_dib8000_get_slave_frontend __kstrtab_dib8000_get_slave_frontend __kcrctab_dib8000_get_slave_frontend __ksymtab_dib8000_remove_slave_frontend __kstrtab_dib8000_remove_slave_frontend __kcrctab_dib8000_remove_slave_frontend __ksymtab_dib8000_set_slave_frontend __kstrtab_dib8000_set_slave_frontend __kcrctab_dib8000_set_slave_frontend __ksymtab_dib8000_set_tune_state __kstrtab_dib8000_set_tune_state __kcrctab_dib8000_set_tune_state __ksymtab_dib8000_get_tune_state __kstrtab_dib8000_get_tune_state __kcrctab_dib8000_get_tune_state __ksymtab_dib8000_ctrl_timf __kstrtab_dib8000_ctrl_timf __kcrctab_dib8000_ctrl_timf __ksymtab_dib8090p_get_dc_power __kstrtab_dib8090p_get_dc_power __kcrctab_dib8090p_get_dc_power __ksymtab_dib8000_get_adc_power __kstrtab_dib8000_get_adc_power __kcrctab_dib8000_get_adc_power __ksymtab_dib8096p_tuner_sleep __kstrtab_dib8096p_tuner_sleep __kcrctab_dib8096p_tuner_sleep __ksymtab_dib8096p_get_i2c_tuner __kstrtab_dib8096p_get_i2c_tuner __kcrctab_dib8096p_get_i2c_tuner __ksymtab_dib8000_pwm_agc_reset __kstrtab_dib8000_pwm_agc_reset __kcrctab_dib8000_pwm_agc_reset __ksymtab_dib8000_set_gpio __kstrtab_dib8000_set_gpio __kcrctab_dib8000_set_gpio __ksymtab_dib8000_update_pll __kstrtab_dib8000_update_pll __kcrctab_dib8000_update_pll __ksymtab_dib8000_set_wbd_ref __kstrtab_dib8000_set_wbd_ref __kcrctab_dib8000_set_wbd_ref __UNIQUE_ID_debug1 __UNIQUE_ID_debugtype0 __param_debug __param_str_debug adp_Q16 adp_Q64 __UNIQUE_ID_srcversion2 __module_depends ____versions __UNIQUE_ID_intree1 __UNIQUE_ID_vermagic0 dev_get_drvdata dibx000_init_i2c_master __this_module __crc_dib8000_remove_slave_frontend dib8000_set_tune_state dib8000_set_slave_frontend dib8000_attach intlog10 __crc_dib8000_get_slave_frontend kfree __crc_dib8090p_get_dc_power __crc_dib8000_i2c_enumeration kmem_cache_alloc_trace __fentry__ __crc_dib8000_get_tune_state __crc_dib8000_get_adc_power dib8000_ctrl_timf __crc_dib8096p_get_i2c_tuner dibx000_get_i2c_adapter __crc_dib8000_pwm_agc_reset __crc_dib8000_ctrl_timf dib8090p_get_dc_power i2c_del_adapter dib8000_get_adc_power dib8096p_get_i2c_tuner dib8000_update_pll dibx000_reset_i2c_master __crc_dib8000_set_slave_frontend dibx000_exit_i2c_master dib8000_set_gpio __crc_dib8000_pid_filter_ctrl dib8000_get_tune_state __crc_dib8000_get_i2c_master dib8000_set_wbd_ref dib8000_remove_slave_frontend __crc_dib8000_set_tune_state printk __mutex_init mutex_lock_interruptible dvb_frontend_detach __crc_dib8000_attach i2c_add_adapter systime mutex_unlock dib8000_pid_filter_ctrl __crc_dib8000_pid_filter __crc_dib8096p_tuner_sleep dib8096p_tuner_sleep i2c_transfer dib8000_i2c_enumeration dib8000_get_slave_frontend dev_set_drvdata param_ops_int dib8000_pwm_agc_reset dib8000_get_i2c_master dib8000_pid_filter __crc_dib8000_set_wbd_ref msleep __crc_dib8000_update_pll __crc_dib8000_set_gpio kmalloc_caches 1 Q q ! ) A , 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