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I LE1H HLA P HCHID$H@H8HtDH Ht8HH`1HHtхu1H[A\]f H a @ H I|$H 1H H{@ H1 fI|$H 1H @ I|$H H f U HATSH HCxH9Cx E1u!1 HHAD; sHHuEt)LcPL C C L 1[A\]H{H H HwH H H 1H C UH UH H H ]UH H ]%s: Entry
%s: exit, ret: %d
Removed...
Putting desc: %p
Transfer already ongoing
Enabling irq: %d, IER: 0x%x
%s: started %u
tx_submit: queued %u
Too big sg element
Incorrect length: %d
desc: %p, addr: 0x%llx
%s: No SG list
desc %p not ACKed
No descriptor space
Failed to update desc: %d
No platform data
timb-dma Allocated TD: %p
Failed to remap I/O memory
Failed to request IRQ
Wrong channel configuration
Chan: %d, membase: %p
Probe result: %d
descriptor %u complete
Checking irq: %d, td: %p
%s: Freeing desc: %p
Freeing desc: %p
Failed to alloc descriptor
DMA mapping error: %d
%s: entry
timb_dma td_chan: %p, chan: %d, membase: %p
/build/buildd/linux-lts-saucy-3.11.0/drivers/dma/timb_dma.c Requesting channel in wrong direction
Not enough descriptors available
/build/buildd/linux-lts-saucy-3.11.0/include/asm-generic/dma-mapping-common.h Failed to register async device
/build/buildd/linux-lts-saucy-3.11.0/drivers/dma/dmaengine.h Couldnt allocate any descriptors
K L $ 5 dalias=platform:timb-dma author=Pelagicore AB <info@pelagicore.com> description=Timberdale DMA controller driver license=GPL v2 srcversion=E5D0096069995CA317DC044 depends= intree=Y vermagic=3.11.0-15-generic SMP mod_unload modversions td_control td_prep_slave_sg td_issue_pending __td_start_next td_tx_status td_free_chan_resources td_alloc_chan_resources td_tx_submit td_remove td_probe __td_finish td_desc_get td_fill_desc td_desc_put __td_dma_done_ack __td_start_dma __td_enable_chan_irq td_free_desc -#w module_layout FCr platform_driver_unregister ϑ __platform_driver_register (L phys_base EԴY dma_async_tx_descriptor_init kmem_cache_alloc_trace Yc kmalloc_caches pv_lock_ops + _raw_spin_lock jo dev_set_drvdata 6v1 dma_async_device_register r request_threaded_irq mE tasklet_init 5B ioremap_nocache 地 __kmalloc __request_region __tasklet_schedule p4; dma_ops ? sg_next 1m dev_err _ ioread32 y!lC iowrite32 3c _raw_spin_unlock_bh 7 _raw_spin_lock_bh 4a| __release_region Xi iomem_resource z kfree S9 iounmap & tasklet_kill ث
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` & . = C U d { ) 1 K f td_tx_status descriptor.22507 descriptor.22509 __func__.22508 td_remove descriptor.22606 td_desc_put descriptor.22448 __td_start_dma descriptor.22385 descriptor.22343 __td_start_next descriptor.22416 __func__.22417 td_tx_submit descriptor.22430 descriptor.22428 __func__.22429 td_fill_desc.isra.11 descriptor.22377 td_prep_slave_sg descriptor.22463 __func__.22533 dma_unmap_single_attrs.part.13 td_irq td_probe descriptor.22587 td_tasklet td_alloc_chan_resources td_free_chan_resources td_issue_pending td_control descriptor.22595 descriptor.22599 __td_unmap_desc __td_finish descriptor.22396 descriptor.22548 __func__.22549 descriptor.22516 descriptor.22352 __func__.22517 descriptor.22489 descriptor.22497 descriptor.22442 __func__.22490 td_alloc_init_desc descriptor.22474 __func__.22475 td_driver_init td_driver td_driver_exit __UNIQUE_ID_alias3 __UNIQUE_ID_author2 __UNIQUE_ID_description1 __UNIQUE_ID_license0 __func__.22607 __func__.22588 __func__.22397 __func__.22464 __func__.22378 __func__.22449 __func__.22353 __func__.22386 __func__.22344 __func__.22443 .LC7 .LC19 .LC30 __UNIQUE_ID_srcversion2 __module_depends ____versions __UNIQUE_ID_intree1 __UNIQUE_ID_vermagic0 free_irq ioread32 dma_ops dev_get_drvdata iowrite32 platform_driver_unregister __this_module dma_async_device_unregister platform_get_irq iounmap cleanup_module kfree __dynamic_dev_dbg _raw_spin_lock kmem_cache_alloc_trace __release_region __fentry__ init_module _raw_spin_unlock_bh ioremap_nocache tasklet_kill request_threaded_irq tasklet_init platform_get_resource __tasklet_schedule phys_base dev_err dma_async_device_register __platform_driver_register dma_async_tx_descriptor_init sg_next _raw_spin_lock_bh dev_set_drvdata iomem_resource pv_lock_ops __kmalloc kmalloc_caches __request_region p M ` u ` 0 l ` X l p c * w 7 h B g M ` Y t e i m k { o l p ] ! r = * D @ O l a p d d a 6 % T d a d s d d d < z l V l ! p D P s l p e : r b = H l s l p . 5 z z l p `
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